/*
 * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
 * 
 * SPDX-License-Identifier: Apache-2.0
 * 
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 * 
 * http://www.apache.org/licenses/LICENSE-2.0
 * 
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 * @file     STM32G030.h
 * @brief    CMSIS HeaderFile
 * @version  1.0
 * @date     22. April 2020
 * @note     Generated by SVDConv V3.2.66 on Wednesday, 22.04.2020 20:14:54
 *           from File 'stm32g030.svd',
 *           last modified on Thursday, 29.08.2019 00:09:56
 */



/** @addtogroup 
  * @{
  */


/** @addtogroup STM32G030
  * @{
  */


#ifndef STM32G030_H
#define STM32G030_H

#ifdef __cplusplus
extern "C" {
#endif


/** @addtogroup Configuration_of_CMSIS
  * @{
  */



/* =========================================================================================================================== */
/* ================                                Interrupt Number Definition                                ================ */
/* =========================================================================================================================== */

typedef enum {
/* =======================================  ARM Cortex-M0 Specific Interrupt Numbers  ======================================== */
  Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
  NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
  HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
  SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
  PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
  SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
/* =========================================  STM32G030 Specific Interrupt Numbers  ========================================== */
  WWDG_IRQn                 =   0,              /*!< 0  Window watchdog interrupt                                              */
  PVD_IRQn                  =   1,              /*!< 1  Power voltage detector interrupt                                       */
  RTC_TAMP_IRQn             =   2,              /*!< 2  RTC and TAMP interrupts                                                */
  FLASH_IRQn                =   3,              /*!< 3  Flash global interrupt                                                 */
  RCC_IRQn                  =   4,              /*!< 4  RCC global interrupt                                                   */
  EXTI0_1_IRQn              =   5,              /*!< 5  EXTI line 0 & 1 interrupt                                              */
  EXTI2_3_IRQn              =   6,              /*!< 6  EXTI line 2 & 3 interrupt                                              */
  EXTI4_15_IRQn             =   7,              /*!< 7  EXTI line 4 to 15 interrupt                                            */
  DMA_Channel1_IRQn         =   9,              /*!< 9  DMA channel 1 interrupt                                                */
  DMA_Channel2_3_IRQn       =  10,              /*!< 10 DMA channel 2 & 3 interrupts                                           */
  DMA_Channel4_5_6_7_IRQn   =  11,              /*!< 11 DMA channel 4, 5, 6 & 7 and DMAMUX                                     */
  ADC_COMP_IRQn             =  12,              /*!< 12 ADC and COMP interrupts                                                */
  TIM1_BRK_UP_TRG_COM_IRQn  =  13,              /*!< 13 TIM1 break, update, trigger                                            */
  TIM1_CC_IRQn              =  14,              /*!< 14 TIM1 Capture Compare interrupt                                         */
  TIM2_IRQn                 =  15,              /*!< 15 TIM2 global interrupt                                                  */
  TIM3_IRQn                 =  16,              /*!< 16 TIM3 global interrupt                                                  */
  TIM14_IRQn                =  19,              /*!< 19 TIM14 global interrupt                                                 */
  TIM16_IRQn                =  21,              /*!< 21 TIM16 global interrupt                                                 */
  TIM17_IRQn                =  22,              /*!< 22 TIM17 global interrupt                                                 */
  I2C1_IRQn                 =  23,              /*!< 23 I2C1 global interrupt                                                  */
  I2C2_IRQn                 =  24,              /*!< 24 I2C2 global interrupt                                                  */
  SPI1_IRQn                 =  25,              /*!< 25 SPI1 global interrupt                                                  */
  SPI2_IRQn                 =  26,              /*!< 26 SPI2 global interrupt                                                  */
  USART1_IRQn               =  27,              /*!< 27 USART1 global interrupt                                                */
  USART2_IRQn               =  28,              /*!< 28 USART2 global interrupt                                                */
  USART3_USART4_LPUART1_IRQn=  29,              /*!< 29 USART3 + USART4 + LPUART1                                              */
  CEC_IRQn                  =  30,              /*!< 30 CEC global interrupt                                                   */
  AES_RNG_IRQn              =  31               /*!< 31 AES and RNG global interrupts                                          */
} IRQn_Type;



/* =========================================================================================================================== */
/* ================                           Processor and Core Peripheral Section                           ================ */
/* =========================================================================================================================== */

/* ===========================  Configuration of the ARM Cortex-M0 Processor and Core Peripherals  =========================== */
#define __CM0_REV                 0x0001U       /*!< CM0 Core Revision                                                         */
#define __NVIC_PRIO_BITS               4        /*!< Number of Bits used for Priority Levels                                   */
#define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */


/** @} */ /* End of group Configuration_of_CMSIS */

#include "core_cm0.h"                           /*!< ARM Cortex-M0 processor and core peripherals                              */
#include "system_STM32G030.h"                   /*!< STM32G030 System                                                          */

#ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __IM   __I
#endif
#ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __OM   __O
#endif
#ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
  #define __IOM  __IO
#endif


/* ========================================  Start of section using anonymous unions  ======================================== */
#if defined (__CC_ARM)
  #pragma push
  #pragma anon_unions
#elif defined (__ICCARM__)
  #pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wc11-extensions"
  #pragma clang diagnostic ignored "-Wreserved-id-macro"
  #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
  #pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning 586
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif


/* =========================================================================================================================== */
/* ================                            Device Specific Peripheral Section                             ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                           IWDG                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Independent watchdog (IWDG)
  */

typedef struct {                                /*!< (@ 0x40003000) IWDG Structure                                             */
  __OM  uint32_t  KR;                           /*!< (@ 0x00000000) Key register                                               */
  __IOM uint32_t  PR;                           /*!< (@ 0x00000004) Prescaler register                                         */
  __IOM uint32_t  RLR;                          /*!< (@ 0x00000008) Reload register                                            */
  __IM  uint32_t  SR;                           /*!< (@ 0x0000000C) Status register                                            */
  __IOM uint32_t  WINR;                         /*!< (@ 0x00000010) Window register                                            */
} IWDG_Type;                                    /*!< Size = 20 (0x14)                                                          */



/* =========================================================================================================================== */
/* ================                                           WWDG                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief System window watchdog (WWDG)
  */

typedef struct {                                /*!< (@ 0x40002C00) WWDG Structure                                             */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000000) Control register                                           */
  __IOM uint32_t  CFR;                          /*!< (@ 0x00000004) Configuration register                                     */
  __IOM uint32_t  SR;                           /*!< (@ 0x00000008) Status register                                            */
} WWDG_Type;                                    /*!< Size = 12 (0xc)                                                           */



/* =========================================================================================================================== */
/* ================                                           FLASH                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Flash (FLASH)
  */

typedef struct {                                /*!< (@ 0x40022000) FLASH Structure                                            */
  __IOM uint32_t  ACR;                          /*!< (@ 0x00000000) Access control register                                    */
  __IM  uint32_t  RESERVED;
  __OM  uint32_t  KEYR;                         /*!< (@ 0x00000008) Flash key register                                         */
  __OM  uint32_t  OPTKEYR;                      /*!< (@ 0x0000000C) Option byte key register                                   */
  __IOM uint32_t  SR;                           /*!< (@ 0x00000010) Status register                                            */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000014) Flash control register                                     */
  __IOM uint32_t  ECCR;                         /*!< (@ 0x00000018) Flash ECC register                                         */
  __IM  uint32_t  RESERVED1;
  __IOM uint32_t  OPTR;                         /*!< (@ 0x00000020) Flash option register                                      */
  __IM  uint32_t  PCROP1ASR;                    /*!< (@ 0x00000024) Flash PCROP zone A Start address register                  */
  __IM  uint32_t  PCROP1AER;                    /*!< (@ 0x00000028) Flash PCROP zone A End address register                    */
  __IM  uint32_t  WRP1AR;                       /*!< (@ 0x0000002C) Flash WRP area A address register                          */
  __IM  uint32_t  WRP1BR;                       /*!< (@ 0x00000030) Flash WRP area B address register                          */
  __IM  uint32_t  PCROP1BSR;                    /*!< (@ 0x00000034) Flash PCROP zone B Start address register                  */
  __IM  uint32_t  PCROP1BER;                    /*!< (@ 0x00000038) Flash PCROP zone B End address register                    */
  __IM  uint32_t  RESERVED2[17];
  __IM  uint32_t  SECR;                         /*!< (@ 0x00000080) Flash Security register                                    */
} FLASH_Type;                                   /*!< Size = 132 (0x84)                                                         */



/* =========================================================================================================================== */
/* ================                                            RCC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Reset and clock control (RCC)
  */

typedef struct {                                /*!< (@ 0x40021000) RCC Structure                                              */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000000) Clock control register                                     */
  __IOM uint32_t  ICSCR;                        /*!< (@ 0x00000004) Internal clock sources calibration register                */
  __IOM uint32_t  CFGR;                         /*!< (@ 0x00000008) Clock configuration register                               */
  __IOM uint32_t  PLLSYSCFGR;                   /*!< (@ 0x0000000C) PLL configuration register                                 */
  __IM  uint32_t  RESERVED[2];
  __IOM uint32_t  CIER;                         /*!< (@ 0x00000018) Clock interrupt enable register                            */
  __IM  uint32_t  CIFR;                         /*!< (@ 0x0000001C) Clock interrupt flag register                              */
  __OM  uint32_t  CICR;                         /*!< (@ 0x00000020) Clock interrupt clear register                             */
  __IOM uint32_t  IOPRSTR;                      /*!< (@ 0x00000024) GPIO reset register                                        */
  __IOM uint32_t  AHBRSTR;                      /*!< (@ 0x00000028) AHB peripheral reset register                              */
  __IOM uint32_t  APBRSTR1;                     /*!< (@ 0x0000002C) APB peripheral reset register 1                            */
  __IOM uint32_t  APBRSTR2;                     /*!< (@ 0x00000030) APB peripheral reset register 2                            */
  __IOM uint32_t  IOPENR;                       /*!< (@ 0x00000034) GPIO clock enable register                                 */
  __IOM uint32_t  AHBENR;                       /*!< (@ 0x00000038) AHB peripheral clock enable register                       */
  __IOM uint32_t  APBENR1;                      /*!< (@ 0x0000003C) APB peripheral clock enable register 1                     */
  __IOM uint32_t  APBENR2;                      /*!< (@ 0x00000040) APB peripheral clock enable register 2                     */
  __IOM uint32_t  IOPSMENR;                     /*!< (@ 0x00000044) GPIO in Sleep mode clock enable register                   */
  __IOM uint32_t  AHBSMENR;                     /*!< (@ 0x00000048) AHB peripheral clock enable in Sleep mode register         */
  __IOM uint32_t  APBSMENR1;                    /*!< (@ 0x0000004C) APB peripheral clock enable in Sleep mode register
                                                                    1                                                          */
  __IOM uint32_t  APBSMENR2;                    /*!< (@ 0x00000050) APB peripheral clock enable in Sleep mode register
                                                                    2                                                          */
  __IOM uint32_t  CCIPR;                        /*!< (@ 0x00000054) Peripherals independent clock configuration register       */
  __IM  uint32_t  RESERVED1;
  __IOM uint32_t  BDCR;                         /*!< (@ 0x0000005C) RTC domain control register                                */
  __IOM uint32_t  CSR;                          /*!< (@ 0x00000060) Control/status register                                    */
} RCC_Type;                                     /*!< Size = 100 (0x64)                                                         */



/* =========================================================================================================================== */
/* ================                                            PWR                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Power control (PWR)
  */

typedef struct {                                /*!< (@ 0x40007000) PWR Structure                                              */
  __IOM uint32_t  CR1;                          /*!< (@ 0x00000000) Power control register 1                                   */
  __IOM uint32_t  CR2;                          /*!< (@ 0x00000004) Power control register 2                                   */
  __IOM uint32_t  CR3;                          /*!< (@ 0x00000008) Power control register 3                                   */
  __IOM uint32_t  CR4;                          /*!< (@ 0x0000000C) Power control register 4                                   */
  __IM  uint32_t  SR1;                          /*!< (@ 0x00000010) Power status register 1                                    */
  __IM  uint32_t  SR2;                          /*!< (@ 0x00000014) Power status register 2                                    */
  __OM  uint32_t  SCR;                          /*!< (@ 0x00000018) Power status clear register                                */
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  PUCRA;                        /*!< (@ 0x00000020) Power Port A pull-up control register                      */
  __IOM uint32_t  PDCRA;                        /*!< (@ 0x00000024) Power Port A pull-down control register                    */
  __IOM uint32_t  PUCRB;                        /*!< (@ 0x00000028) Power Port B pull-up control register                      */
  __IOM uint32_t  PDCRB;                        /*!< (@ 0x0000002C) Power Port B pull-down control register                    */
  __IOM uint32_t  PUCRC;                        /*!< (@ 0x00000030) Power Port C pull-up control register                      */
  __IOM uint32_t  PDCRC;                        /*!< (@ 0x00000034) Power Port C pull-down control register                    */
  __IOM uint32_t  PUCRD;                        /*!< (@ 0x00000038) Power Port D pull-up control register                      */
  __IOM uint32_t  PDCRD;                        /*!< (@ 0x0000003C) Power Port D pull-down control register                    */
  __IM  uint32_t  RESERVED1[2];
  __IOM uint32_t  PUCRF;                        /*!< (@ 0x00000048) Power Port F pull-up control register                      */
  __IOM uint32_t  PDCRF;                        /*!< (@ 0x0000004C) Power Port F pull-down control register                    */
} PWR_Type;                                     /*!< Size = 80 (0x50)                                                          */



/* =========================================================================================================================== */
/* ================                                            DMA                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief DMA controller (DMA)
  */

typedef struct {                                /*!< (@ 0x40020000) DMA Structure                                              */
  __IM  uint32_t  ISR;                          /*!< (@ 0x00000000) low interrupt status register                              */
  __IM  uint32_t  IFCR;                         /*!< (@ 0x00000004) high interrupt status register                             */
  __IOM uint32_t  CCR1;                         /*!< (@ 0x00000008) DMA channel x configuration register                       */
  __IOM uint32_t  CNDTR1;                       /*!< (@ 0x0000000C) DMA channel x number of data register                      */
  __IOM uint32_t  CPAR1;                        /*!< (@ 0x00000010) DMA channel x peripheral address register                  */
  __IOM uint32_t  CMAR1;                        /*!< (@ 0x00000014) DMA channel x memory address register                      */
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  CCR2;                         /*!< (@ 0x0000001C) DMA channel x configuration register                       */
  __IOM uint32_t  CNDTR2;                       /*!< (@ 0x00000020) DMA channel x number of data register                      */
  __IOM uint32_t  CPAR2;                        /*!< (@ 0x00000024) DMA channel x peripheral address register                  */
  __IOM uint32_t  CMAR2;                        /*!< (@ 0x00000028) DMA channel x memory address register                      */
  __IM  uint32_t  RESERVED1;
  __IOM uint32_t  CCR3;                         /*!< (@ 0x00000030) DMA channel x configuration register                       */
  __IOM uint32_t  CNDTR3;                       /*!< (@ 0x00000034) DMA channel x configuration register                       */
  __IOM uint32_t  CPAR3;                        /*!< (@ 0x00000038) DMA channel x peripheral address register                  */
  __IOM uint32_t  CMAR3;                        /*!< (@ 0x0000003C) DMA channel x memory address register                      */
  __IM  uint32_t  RESERVED2;
  __IOM uint32_t  CCR4;                         /*!< (@ 0x00000044) DMA channel x configuration register                       */
  __IOM uint32_t  CNDTR4;                       /*!< (@ 0x00000048) DMA channel x configuration register                       */
  __IOM uint32_t  CPAR4;                        /*!< (@ 0x0000004C) DMA channel x peripheral address register                  */
  __IOM uint32_t  CMAR4;                        /*!< (@ 0x00000050) DMA channel x memory address register                      */
  __IM  uint32_t  RESERVED3;
  __IOM uint32_t  CCR5;                         /*!< (@ 0x00000058) DMA channel x configuration register                       */
  __IOM uint32_t  CNDTR5;                       /*!< (@ 0x0000005C) DMA channel x configuration register                       */
  __IOM uint32_t  CPAR5;                        /*!< (@ 0x00000060) DMA channel x peripheral address register                  */
  __IOM uint32_t  CMAR5;                        /*!< (@ 0x00000064) DMA channel x memory address register                      */
} DMA_Type;                                     /*!< Size = 104 (0x68)                                                         */



/* =========================================================================================================================== */
/* ================                                          DMAMUX                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief DMAMUX (DMAMUX)
  */

typedef struct {                                /*!< (@ 0x40020800) DMAMUX Structure                                           */
  __IOM uint32_t  C0CR;                         /*!< (@ 0x00000000) DMAMux - DMA request line multiplexer channel
                                                                    x control register                                         */
  __IOM uint32_t  C1CR;                         /*!< (@ 0x00000004) DMAMux - DMA request line multiplexer channel
                                                                    x control register                                         */
  __IOM uint32_t  C2CR;                         /*!< (@ 0x00000008) DMAMux - DMA request line multiplexer channel
                                                                    x control register                                         */
  __IOM uint32_t  C3CR;                         /*!< (@ 0x0000000C) DMAMux - DMA request line multiplexer channel
                                                                    x control register                                         */
  __IOM uint32_t  C4CR;                         /*!< (@ 0x00000010) DMAMux - DMA request line multiplexer channel
                                                                    x control register                                         */
  __IOM uint32_t  C5CR;                         /*!< (@ 0x00000014) DMAMux - DMA request line multiplexer channel
                                                                    x control register                                         */
  __IOM uint32_t  C6CR;                         /*!< (@ 0x00000018) DMAMux - DMA request line multiplexer channel
                                                                    x control register                                         */
  __IM  uint32_t  RESERVED[57];
  __IOM uint32_t  RG0CR;                        /*!< (@ 0x00000100) DMAMux - DMA request generator channel x control
                                                                    register                                                   */
  __IOM uint32_t  RG1CR;                        /*!< (@ 0x00000104) DMAMux - DMA request generator channel x control
                                                                    register                                                   */
  __IOM uint32_t  RG2CR;                        /*!< (@ 0x00000108) DMAMux - DMA request generator channel x control
                                                                    register                                                   */
  __IOM uint32_t  RG3CR;                        /*!< (@ 0x0000010C) DMAMux - DMA request generator channel x control
                                                                    register                                                   */
  __IM  uint32_t  RESERVED1[12];
  __IM  uint32_t  RGSR;                         /*!< (@ 0x00000140) DMAMux - DMA request generator status register             */
  __OM  uint32_t  RGCFR;                        /*!< (@ 0x00000144) DMAMux - DMA request generator clear flag register         */
} DMAMUX_Type;                                  /*!< Size = 328 (0x148)                                                        */



/* =========================================================================================================================== */
/* ================                                           GPIOA                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief General-purpose I/Os (GPIOA)
  */

typedef struct {                                /*!< (@ 0x50000000) GPIOA Structure                                            */
  __IOM uint32_t  MODER;                        /*!< (@ 0x00000000) GPIO port mode register                                    */
  __IOM uint32_t  OTYPER;                       /*!< (@ 0x00000004) GPIO port output type register                             */
  __IOM uint32_t  OSPEEDR;                      /*!< (@ 0x00000008) GPIO port output speed register                            */
  __IOM uint32_t  PUPDR;                        /*!< (@ 0x0000000C) GPIO port pull-up/pull-down register                       */
  __IM  uint32_t  IDR;                          /*!< (@ 0x00000010) GPIO port input data register                              */
  __IOM uint32_t  ODR;                          /*!< (@ 0x00000014) GPIO port output data register                             */
  __OM  uint32_t  BSRR;                         /*!< (@ 0x00000018) GPIO port bit set/reset register                           */
  __IOM uint32_t  LCKR;                         /*!< (@ 0x0000001C) GPIO port configuration lock register                      */
  __IOM uint32_t  AFRL;                         /*!< (@ 0x00000020) GPIO alternate function low register                       */
  __IOM uint32_t  AFRH;                         /*!< (@ 0x00000024) GPIO alternate function high register                      */
  __OM  uint32_t  BRR;                          /*!< (@ 0x00000028) port bit reset register                                    */
} GPIOA_Type;                                   /*!< Size = 44 (0x2c)                                                          */



/* =========================================================================================================================== */
/* ================                                           GPIOB                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief General-purpose I/Os (GPIOB)
  */

typedef struct {                                /*!< (@ 0x50000400) GPIOB Structure                                            */
  __IOM uint32_t  MODER;                        /*!< (@ 0x00000000) GPIO port mode register                                    */
  __IOM uint32_t  OTYPER;                       /*!< (@ 0x00000004) GPIO port output type register                             */
  __IOM uint32_t  OSPEEDR;                      /*!< (@ 0x00000008) GPIO port output speed register                            */
  __IOM uint32_t  PUPDR;                        /*!< (@ 0x0000000C) GPIO port pull-up/pull-down register                       */
  __IM  uint32_t  IDR;                          /*!< (@ 0x00000010) GPIO port input data register                              */
  __IOM uint32_t  ODR;                          /*!< (@ 0x00000014) GPIO port output data register                             */
  __OM  uint32_t  BSRR;                         /*!< (@ 0x00000018) GPIO port bit set/reset register                           */
  __IOM uint32_t  LCKR;                         /*!< (@ 0x0000001C) GPIO port configuration lock register                      */
  __IOM uint32_t  AFRL;                         /*!< (@ 0x00000020) GPIO alternate function low register                       */
  __IOM uint32_t  AFRH;                         /*!< (@ 0x00000024) GPIO alternate function high register                      */
  __OM  uint32_t  BRR;                          /*!< (@ 0x00000028) port bit reset register                                    */
} GPIOB_Type;                                   /*!< Size = 44 (0x2c)                                                          */



/* =========================================================================================================================== */
/* ================                                            AES                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Advanced encryption standard hardware  accelerator 1 (AES)
  */

typedef struct {                                /*!< (@ 0x40026000) AES Structure                                              */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000000) control register                                           */
  __IM  uint32_t  SR;                           /*!< (@ 0x00000004) status register                                            */
  __IOM uint32_t  DINR;                         /*!< (@ 0x00000008) data input register                                        */
  __IM  uint32_t  DOUTR;                        /*!< (@ 0x0000000C) data output register                                       */
  __IOM uint32_t  KEYR0;                        /*!< (@ 0x00000010) key register 0                                             */
  __IOM uint32_t  KEYR1;                        /*!< (@ 0x00000014) key register 1                                             */
  __IOM uint32_t  KEYR2;                        /*!< (@ 0x00000018) key register 2                                             */
  __IOM uint32_t  KEYR3;                        /*!< (@ 0x0000001C) key register 3                                             */
  __IOM uint32_t  IVR0;                         /*!< (@ 0x00000020) initialization vector register 0                           */
  __IOM uint32_t  IVR1;                         /*!< (@ 0x00000024) initialization vector register 1                           */
  __IOM uint32_t  IVR2;                         /*!< (@ 0x00000028) initialization vector register 2                           */
  __IOM uint32_t  IVR3;                         /*!< (@ 0x0000002C) initialization vector register 3                           */
  __IOM uint32_t  KEYR4;                        /*!< (@ 0x00000030) key register 4                                             */
  __IOM uint32_t  KEYR5;                        /*!< (@ 0x00000034) key register 5                                             */
  __IOM uint32_t  KEYR6;                        /*!< (@ 0x00000038) key register 6                                             */
  __IOM uint32_t  KEYR7;                        /*!< (@ 0x0000003C) key register 7                                             */
  __IOM uint32_t  SUSP0R;                       /*!< (@ 0x00000040) AES suspend register 0                                     */
  __IOM uint32_t  SUSP1R;                       /*!< (@ 0x00000044) AES suspend register 1                                     */
  __IOM uint32_t  SUSP2R;                       /*!< (@ 0x00000048) AES suspend register 2                                     */
  __IOM uint32_t  SUSP3R;                       /*!< (@ 0x0000004C) AES suspend register 3                                     */
  __IOM uint32_t  SUSP4R;                       /*!< (@ 0x00000050) AES suspend register 4                                     */
  __IOM uint32_t  SUSP5R;                       /*!< (@ 0x00000054) AES suspend register 5                                     */
  __IOM uint32_t  SUSP6R;                       /*!< (@ 0x00000058) AES suspend register 6                                     */
  __IOM uint32_t  SUSP7R;                       /*!< (@ 0x0000005C) AES suspend register 7                                     */
} AES_Type;                                     /*!< Size = 96 (0x60)                                                          */



/* =========================================================================================================================== */
/* ================                                            RNG                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Random number generator (RNG)
  */

typedef struct {                                /*!< (@ 0x40025000) RNG Structure                                              */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000000) control register                                           */
  __IOM uint32_t  SR;                           /*!< (@ 0x00000004) status register                                            */
  __IM  uint32_t  DR;                           /*!< (@ 0x00000008) data register                                              */
} RNG_Type;                                     /*!< Size = 12 (0xc)                                                           */



/* =========================================================================================================================== */
/* ================                                            CRC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Cyclic redundancy check calculation  unit (CRC)
  */

typedef struct {                                /*!< (@ 0x40023000) CRC Structure                                              */
  __IOM uint32_t  DR;                           /*!< (@ 0x00000000) Data register                                              */
  __IOM uint32_t  IDR;                          /*!< (@ 0x00000004) Independent data register                                  */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000008) Control register                                           */
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  INIT;                         /*!< (@ 0x00000010) Initial CRC value                                          */
  __IOM uint32_t  POL;                          /*!< (@ 0x00000014) polynomial                                                 */
} CRC_Type;                                     /*!< Size = 24 (0x18)                                                          */



/* =========================================================================================================================== */
/* ================                                           EXTI                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief External interrupt/event  controller (EXTI)
  */

typedef struct {                                /*!< (@ 0x40021800) EXTI Structure                                             */
  __IOM uint32_t  RTSR1;                        /*!< (@ 0x00000000) EXTI rising trigger selection register                     */
  __IOM uint32_t  FTSR1;                        /*!< (@ 0x00000004) EXTI falling trigger selection register                    */
  __IOM uint32_t  SWIER1;                       /*!< (@ 0x00000008) EXTI software interrupt event register                     */
  __IOM uint32_t  RPR1;                         /*!< (@ 0x0000000C) EXTI rising edge pending register                          */
  __IOM uint32_t  FPR1;                         /*!< (@ 0x00000010) EXTI falling edge pending register                         */
  __IM  uint32_t  RESERVED[19];
  __IOM uint32_t  EXTICR1;                      /*!< (@ 0x00000060) EXTI external interrupt selection register                 */
  __IOM uint32_t  EXTICR2;                      /*!< (@ 0x00000064) EXTI external interrupt selection register                 */
  __IOM uint32_t  EXTICR3;                      /*!< (@ 0x00000068) EXTI external interrupt selection register                 */
  __IOM uint32_t  EXTICR4;                      /*!< (@ 0x0000006C) EXTI external interrupt selection register                 */
  __IM  uint32_t  RESERVED1[4];
  __IOM uint32_t  IMR1;                         /*!< (@ 0x00000080) EXTI CPU wakeup with interrupt mask register               */
  __IOM uint32_t  EMR1;                         /*!< (@ 0x00000084) EXTI CPU wakeup with event mask register                   */
} EXTI_Type;                                    /*!< Size = 136 (0x88)                                                         */



/* =========================================================================================================================== */
/* ================                                           TIM16                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief General purpose timers (TIM16)
  */

typedef struct {                                /*!< (@ 0x40014400) TIM16 Structure                                            */
  __IOM uint32_t  CR1;                          /*!< (@ 0x00000000) control register 1                                         */
  __IOM uint32_t  CR2;                          /*!< (@ 0x00000004) control register 2                                         */
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  DIER;                         /*!< (@ 0x0000000C) DMA/Interrupt enable register                              */
  __IOM uint32_t  SR;                           /*!< (@ 0x00000010) status register                                            */
  __OM  uint32_t  EGR;                          /*!< (@ 0x00000014) event generation register                                  */
  
  union {
    __IOM uint32_t CCMR1_Output;                /*!< (@ 0x00000018) capture/compare mode register (output mode)                */
    __IOM uint32_t CCMR1_Input;                 /*!< (@ 0x00000018) capture/compare mode register 1 (input mode)               */
  };
  __IM  uint32_t  RESERVED1;
  __IOM uint32_t  CCER;                         /*!< (@ 0x00000020) capture/compare enable register                            */
  __IOM uint32_t  CNT;                          /*!< (@ 0x00000024) counter                                                    */
  __IOM uint32_t  PSC;                          /*!< (@ 0x00000028) prescaler                                                  */
  __IOM uint32_t  ARR;                          /*!< (@ 0x0000002C) auto-reload register                                       */
  __IOM uint32_t  RCR;                          /*!< (@ 0x00000030) repetition counter register                                */
  __IOM uint32_t  CCR1;                         /*!< (@ 0x00000034) capture/compare register 1                                 */
  __IM  uint32_t  RESERVED2[3];
  __IOM uint32_t  BDTR;                         /*!< (@ 0x00000044) break and dead-time register                               */
  __IOM uint32_t  DCR;                          /*!< (@ 0x00000048) DMA control register                                       */
  __IOM uint32_t  DMAR;                         /*!< (@ 0x0000004C) DMA address for full transfer                              */
  __IM  uint32_t  RESERVED3[4];
  __IOM uint32_t  AF1;                          /*!< (@ 0x00000060) TIM17 option register 1                                    */
  __IM  uint32_t  RESERVED4;
  __IOM uint32_t  TISEL;                        /*!< (@ 0x00000068) input selection register                                   */
} TIM16_Type;                                   /*!< Size = 108 (0x6c)                                                         */



/* =========================================================================================================================== */
/* ================                                          USART1                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Universal synchronous asynchronous receiver  transmitter (USART1)
  */

typedef struct {                                /*!< (@ 0x40013800) USART1 Structure                                           */
  __IOM uint32_t  CR1;                          /*!< (@ 0x00000000) Control register 1                                         */
  __IOM uint32_t  CR2;                          /*!< (@ 0x00000004) Control register 2                                         */
  __IOM uint32_t  CR3;                          /*!< (@ 0x00000008) Control register 3                                         */
  __IOM uint32_t  BRR;                          /*!< (@ 0x0000000C) Baud rate register                                         */
  __IOM uint32_t  GTPR;                         /*!< (@ 0x00000010) Guard time and prescaler register                          */
  __IOM uint32_t  RTOR;                         /*!< (@ 0x00000014) Receiver timeout register                                  */
  __OM  uint32_t  RQR;                          /*!< (@ 0x00000018) Request register                                           */
  __IM  uint32_t  ISR;                          /*!< (@ 0x0000001C) Interrupt & status register                                */
  __OM  uint32_t  ICR;                          /*!< (@ 0x00000020) Interrupt flag clear register                              */
  __IM  uint32_t  RDR;                          /*!< (@ 0x00000024) Receive data register                                      */
  __IOM uint32_t  TDR;                          /*!< (@ 0x00000028) Transmit data register                                     */
  __IOM uint32_t  PRESC;                        /*!< (@ 0x0000002C) Prescaler register                                         */
} USART1_Type;                                  /*!< Size = 48 (0x30)                                                          */



/* =========================================================================================================================== */
/* ================                                           SPI1                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Serial peripheral interface/Inter-IC  sound (SPI1)
  */

typedef struct {                                /*!< (@ 0x40013000) SPI1 Structure                                             */
  __IOM uint32_t  CR1;                          /*!< (@ 0x00000000) control register 1                                         */
  __IOM uint32_t  CR2;                          /*!< (@ 0x00000004) control register 2                                         */
  __IOM uint32_t  SR;                           /*!< (@ 0x00000008) status register                                            */
  __IOM uint32_t  DR;                           /*!< (@ 0x0000000C) data register                                              */
  __IOM uint32_t  CRCPR;                        /*!< (@ 0x00000010) CRC polynomial register                                    */
  __IM  uint32_t  RXCRCR;                       /*!< (@ 0x00000014) RX CRC register                                            */
  __IM  uint32_t  TXCRCR;                       /*!< (@ 0x00000018) TX CRC register                                            */
  __IOM uint32_t  I2SCFGR;                      /*!< (@ 0x0000001C) configuration register                                     */
  __IOM uint32_t  I2SPR;                        /*!< (@ 0x00000020) prescaler register                                         */
} SPI1_Type;                                    /*!< Size = 36 (0x24)                                                          */



/* =========================================================================================================================== */
/* ================                                           TIM1                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Advanced-timers (TIM1)
  */

typedef struct {                                /*!< (@ 0x40012C00) TIM1 Structure                                             */
  __IOM uint32_t  CR1;                          /*!< (@ 0x00000000) control register 1                                         */
  __IOM uint32_t  CR2;                          /*!< (@ 0x00000004) control register 2                                         */
  __IOM uint32_t  SMCR;                         /*!< (@ 0x00000008) slave mode control register                                */
  __IOM uint32_t  DIER;                         /*!< (@ 0x0000000C) DMA/Interrupt enable register                              */
  __IOM uint32_t  SR;                           /*!< (@ 0x00000010) status register                                            */
  __OM  uint32_t  EGR;                          /*!< (@ 0x00000014) event generation register                                  */
  
  union {
    __IOM uint32_t CCMR1_Output;                /*!< (@ 0x00000018) capture/compare mode register 1 (output mode)              */
    __IOM uint32_t CCMR1_Input;                 /*!< (@ 0x00000018) capture/compare mode register 1 (output mode)              */
  };
  
  union {
    __IOM uint32_t CCMR2_Output;                /*!< (@ 0x0000001C) capture/compare mode register 2 (output mode)              */
    __IOM uint32_t CCMR2_Input;                 /*!< (@ 0x0000001C) capture/compare mode register 2 (output mode)              */
  };
  __IOM uint32_t  CCER;                         /*!< (@ 0x00000020) capture/compare enable register                            */
  __IOM uint32_t  CNT;                          /*!< (@ 0x00000024) counter                                                    */
  __IOM uint32_t  PSC;                          /*!< (@ 0x00000028) prescaler                                                  */
  __IOM uint32_t  ARR;                          /*!< (@ 0x0000002C) auto-reload register                                       */
  __IOM uint32_t  RCR;                          /*!< (@ 0x00000030) repetition counter register                                */
  __IOM uint32_t  CCR1;                         /*!< (@ 0x00000034) capture/compare register 1                                 */
  __IOM uint32_t  CCR2;                         /*!< (@ 0x00000038) capture/compare register 2                                 */
  __IOM uint32_t  CCR3;                         /*!< (@ 0x0000003C) capture/compare register 3                                 */
  __IOM uint32_t  CCR4;                         /*!< (@ 0x00000040) capture/compare register 4                                 */
  __IOM uint32_t  BDTR;                         /*!< (@ 0x00000044) break and dead-time register                               */
  __IOM uint32_t  DCR;                          /*!< (@ 0x00000048) DMA control register                                       */
  __IOM uint32_t  DMAR;                         /*!< (@ 0x0000004C) DMA address for full transfer                              */
  __IOM uint32_t  OR1;                          /*!< (@ 0x00000050) option register 1                                          */
  __IOM uint32_t  CCMR3_Output;                 /*!< (@ 0x00000054) capture/compare mode register 2 (output mode)              */
  __IOM uint32_t  CCR5;                         /*!< (@ 0x00000058) capture/compare register 4                                 */
  __IOM uint32_t  CCR6;                         /*!< (@ 0x0000005C) capture/compare register 4                                 */
  __IOM uint32_t  AF1;                          /*!< (@ 0x00000060) DMA address for full transfer                              */
  __IOM uint32_t  AF2;                          /*!< (@ 0x00000064) DMA address for full transfer                              */
  __IOM uint32_t  TISEL;                        /*!< (@ 0x00000068) TIM1 timer input selection register                        */
} TIM1_Type;                                    /*!< Size = 108 (0x6c)                                                         */



/* =========================================================================================================================== */
/* ================                                            ADC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Analog to Digital Converter instance  1 (ADC)
  */

typedef struct {                                /*!< (@ 0x40012400) ADC Structure                                              */
  __IOM uint32_t  ISR;                          /*!< (@ 0x00000000) ADC interrupt and status register                          */
  __IOM uint32_t  IER;                          /*!< (@ 0x00000004) ADC interrupt enable register                              */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000008) ADC control register                                       */
  __IOM uint32_t  CFGR1;                        /*!< (@ 0x0000000C) ADC configuration register 1                               */
  __IOM uint32_t  CFGR2;                        /*!< (@ 0x00000010) ADC configuration register 2                               */
  __IOM uint32_t  SMPR;                         /*!< (@ 0x00000014) ADC sampling time register                                 */
  __IM  uint32_t  RESERVED[2];
  __IOM uint32_t  AWD1TR;                       /*!< (@ 0x00000020) watchdog threshold register                                */
  __IOM uint32_t  AWD2TR;                       /*!< (@ 0x00000024) watchdog threshold register                                */
  
  union {
    __IOM uint32_t CHSELR;                      /*!< (@ 0x00000028) channel selection register                                 */
    __IOM uint32_t CHSELR_1;                    /*!< (@ 0x00000028) channel selection register CHSELRMOD = 1 in ADC_CFGR1      */
  };
  __IOM uint32_t  AWD3TR;                       /*!< (@ 0x0000002C) watchdog threshold register                                */
  __IM  uint32_t  RESERVED1[4];
  __IM  uint32_t  DR;                           /*!< (@ 0x00000040) ADC group regular conversion data register                 */
  __IM  uint32_t  RESERVED2[23];
  __IOM uint32_t  AWD2CR;                       /*!< (@ 0x000000A0) ADC analog watchdog 2 configuration register               */
  __IOM uint32_t  AWD3CR;                       /*!< (@ 0x000000A4) ADC analog watchdog 3 configuration register               */
  __IM  uint32_t  RESERVED3[3];
  __IOM uint32_t  CALFACT;                      /*!< (@ 0x000000B4) ADC calibration factors register                           */
  __IM  uint32_t  RESERVED4[148];
  __IOM uint32_t  CCR;                          /*!< (@ 0x00000308) ADC common control register                                */
} ADC_Type;                                     /*!< Size = 780 (0x30c)                                                        */



/* =========================================================================================================================== */
/* ================                                          SYSCFG                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief System configuration controller (SYSCFG)
  */

typedef struct {                                /*!< (@ 0x40010000) SYSCFG Structure                                           */
  __IOM uint32_t  CFGR1;                        /*!< (@ 0x00000000) SYSCFG configuration register 1                            */
  __IM  uint32_t  RESERVED[5];
  __IOM uint32_t  CFGR2;                        /*!< (@ 0x00000018) SYSCFG configuration register 1                            */
} SYSCFG_Type;                                  /*!< Size = 28 (0x1c)                                                          */



/* =========================================================================================================================== */
/* ================                                           TAMP                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Tamper and backup registers (TAMP)
  */

typedef struct {                                /*!< (@ 0x4000B000) TAMP Structure                                             */
  __IOM uint32_t  CR1;                          /*!< (@ 0x00000000) control register 1                                         */
  __IOM uint32_t  CR2;                          /*!< (@ 0x00000004) control register 2                                         */
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  FLTCR;                        /*!< (@ 0x0000000C) TAMP filter control register                               */
  __IM  uint32_t  RESERVED1[7];
  __IOM uint32_t  IER;                          /*!< (@ 0x0000002C) TAMP interrupt enable register                             */
  __IM  uint32_t  SR;                           /*!< (@ 0x00000030) TAMP status register                                       */
  __IM  uint32_t  MISR;                         /*!< (@ 0x00000034) TAMP masked interrupt status register                      */
  __IM  uint32_t  RESERVED2;
  __OM  uint32_t  SCR;                          /*!< (@ 0x0000003C) TAMP status clear register                                 */
  __IM  uint32_t  RESERVED3[48];
  __IOM uint32_t  BKP0R;                        /*!< (@ 0x00000100) TAMP backup register                                       */
  __IOM uint32_t  BKP1R;                        /*!< (@ 0x00000104) TAMP backup register                                       */
  __IOM uint32_t  BKP2R;                        /*!< (@ 0x00000108) TAMP backup register                                       */
  __IOM uint32_t  BKP3R;                        /*!< (@ 0x0000010C) TAMP backup register                                       */
  __IOM uint32_t  BKP4R;                        /*!< (@ 0x00000110) TAMP backup register                                       */
} TAMP_Type;                                    /*!< Size = 276 (0x114)                                                        */



/* =========================================================================================================================== */
/* ================                                          LPTIM1                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Low power timer (LPTIM1)
  */

typedef struct {                                /*!< (@ 0x40007C00) LPTIM1 Structure                                           */
  __IM  uint32_t  ISR;                          /*!< (@ 0x00000000) Interrupt and Status Register                              */
  __OM  uint32_t  ICR;                          /*!< (@ 0x00000004) Interrupt Clear Register                                   */
  __IOM uint32_t  IER;                          /*!< (@ 0x00000008) Interrupt Enable Register                                  */
  __IOM uint32_t  CFGR;                         /*!< (@ 0x0000000C) Configuration Register                                     */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000010) Control Register                                           */
  __IOM uint32_t  CMP;                          /*!< (@ 0x00000014) Compare Register                                           */
  __IOM uint32_t  ARR;                          /*!< (@ 0x00000018) Autoreload Register                                        */
  __IM  uint32_t  CNT;                          /*!< (@ 0x0000001C) Counter Register                                           */
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  CFGR2;                        /*!< (@ 0x00000024) LPTIM configuration register 2                             */
} LPTIM1_Type;                                  /*!< Size = 40 (0x28)                                                          */



/* =========================================================================================================================== */
/* ================                                          LPUART                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Universal synchronous asynchronous receiver  transmitter (LPUART)
  */

typedef struct {                                /*!< (@ 0x40008000) LPUART Structure                                           */
  __IOM uint32_t  CR1;                          /*!< (@ 0x00000000) Control register 1                                         */
  __IOM uint32_t  CR2;                          /*!< (@ 0x00000004) Control register 2                                         */
  __IOM uint32_t  CR3;                          /*!< (@ 0x00000008) Control register 3                                         */
  __IOM uint32_t  BRR;                          /*!< (@ 0x0000000C) Baud rate register                                         */
  __IM  uint32_t  RESERVED[2];
  __OM  uint32_t  RQR;                          /*!< (@ 0x00000018) Request register                                           */
  __IM  uint32_t  ISR;                          /*!< (@ 0x0000001C) Interrupt & status register                                */
  __OM  uint32_t  ICR;                          /*!< (@ 0x00000020) Interrupt flag clear register                              */
  __IM  uint32_t  RDR;                          /*!< (@ 0x00000024) Receive data register                                      */
  __IOM uint32_t  TDR;                          /*!< (@ 0x00000028) Transmit data register                                     */
  __IOM uint32_t  PRESC;                        /*!< (@ 0x0000002C) Prescaler register                                         */
} LPUART_Type;                                  /*!< Size = 48 (0x30)                                                          */



/* =========================================================================================================================== */
/* ================                                           I2C1                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Inter-integrated circuit (I2C1)
  */

typedef struct {                                /*!< (@ 0x40005400) I2C1 Structure                                             */
  __IOM uint32_t  CR1;                          /*!< (@ 0x00000000) Control register 1                                         */
  __IOM uint32_t  CR2;                          /*!< (@ 0x00000004) Control register 2                                         */
  __IOM uint32_t  OAR1;                         /*!< (@ 0x00000008) Own address register 1                                     */
  __IOM uint32_t  OAR2;                         /*!< (@ 0x0000000C) Own address register 2                                     */
  __IOM uint32_t  TIMINGR;                      /*!< (@ 0x00000010) Timing register                                            */
  __IOM uint32_t  TIMEOUTR;                     /*!< (@ 0x00000014) Status register 1                                          */
  __IOM uint32_t  ISR;                          /*!< (@ 0x00000018) Interrupt and Status register                              */
  __OM  uint32_t  ICR;                          /*!< (@ 0x0000001C) Interrupt clear register                                   */
  __IM  uint32_t  PECR;                         /*!< (@ 0x00000020) PEC register                                               */
  __IM  uint32_t  RXDR;                         /*!< (@ 0x00000024) Receive data register                                      */
  __IOM uint32_t  TXDR;                         /*!< (@ 0x00000028) Transmit data register                                     */
} I2C1_Type;                                    /*!< Size = 44 (0x2c)                                                          */



/* =========================================================================================================================== */
/* ================                                            RTC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Real-time clock (RTC)
  */

typedef struct {                                /*!< (@ 0x40002800) RTC Structure                                              */
  __IOM uint32_t  TR;                           /*!< (@ 0x00000000) time register                                              */
  __IOM uint32_t  DR;                           /*!< (@ 0x00000004) date register                                              */
  __IM  uint32_t  SSR;                          /*!< (@ 0x00000008) sub second register                                        */
  __IOM uint32_t  ICSR;                         /*!< (@ 0x0000000C) initialization and status register                         */
  __IOM uint32_t  PRER;                         /*!< (@ 0x00000010) prescaler register                                         */
  __IOM uint32_t  WUTR;                         /*!< (@ 0x00000014) wakeup timer register                                      */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000018) control register                                           */
  __IM  uint32_t  RESERVED[2];
  __OM  uint32_t  WPR;                          /*!< (@ 0x00000024) write protection register                                  */
  __IOM uint32_t  CALR;                         /*!< (@ 0x00000028) calibration register                                       */
  __OM  uint32_t  SHIFTR;                       /*!< (@ 0x0000002C) shift control register                                     */
  __IM  uint32_t  TSTR;                         /*!< (@ 0x00000030) time stamp time register                                   */
  __IM  uint32_t  TSDR;                         /*!< (@ 0x00000034) time stamp date register                                   */
  __IM  uint32_t  TSSSR;                        /*!< (@ 0x00000038) timestamp sub second register                              */
  __IM  uint32_t  RESERVED1;
  __IOM uint32_t  ALRMAR;                       /*!< (@ 0x00000040) alarm A register                                           */
  __IOM uint32_t  ALRMASSR;                     /*!< (@ 0x00000044) alarm A sub second register                                */
  __IOM uint32_t  ALRMBR;                       /*!< (@ 0x00000048) alarm B register                                           */
  __IOM uint32_t  ALRMBSSR;                     /*!< (@ 0x0000004C) alarm B sub second register                                */
  __IM  uint32_t  SR;                           /*!< (@ 0x00000050) status register                                            */
  __IM  uint32_t  MISR;                         /*!< (@ 0x00000054) masked interrupt status register                           */
  __IM  uint32_t  RESERVED2;
  __IOM uint32_t  SCR;                          /*!< (@ 0x0000005C) status clear register                                      */
} RTC_Type;                                     /*!< Size = 96 (0x60)                                                          */



/* =========================================================================================================================== */
/* ================                                           TIM14                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief General purpose timers (TIM14)
  */

typedef struct {                                /*!< (@ 0x40002000) TIM14 Structure                                            */
  __IOM uint32_t  CR1;                          /*!< (@ 0x00000000) control register 1                                         */
  __IM  uint32_t  RESERVED[2];
  __IOM uint32_t  DIER;                         /*!< (@ 0x0000000C) DMA/Interrupt enable register                              */
  __IOM uint32_t  SR;                           /*!< (@ 0x00000010) status register                                            */
  __OM  uint32_t  EGR;                          /*!< (@ 0x00000014) event generation register                                  */
  
  union {
    __IOM uint32_t CCMR1_Output;                /*!< (@ 0x00000018) capture/compare mode register 1 (output mode)              */
    __IOM uint32_t CCMR1_Input;                 /*!< (@ 0x00000018) capture/compare mode register 1 (input mode)               */
  };
  __IM  uint32_t  RESERVED1;
  __IOM uint32_t  CCER;                         /*!< (@ 0x00000020) capture/compare enable register                            */
  __IOM uint32_t  CNT;                          /*!< (@ 0x00000024) counter                                                    */
  __IOM uint32_t  PSC;                          /*!< (@ 0x00000028) prescaler                                                  */
  __IOM uint32_t  ARR;                          /*!< (@ 0x0000002C) auto-reload register                                       */
  __IM  uint32_t  RESERVED2;
  __IOM uint32_t  CCR1;                         /*!< (@ 0x00000034) capture/compare register 1                                 */
  __IM  uint32_t  RESERVED3[12];
  __IOM uint32_t  TISEL;                        /*!< (@ 0x00000068) TIM timer input selection register                         */
} TIM14_Type;                                   /*!< Size = 108 (0x6c)                                                         */



/* =========================================================================================================================== */
/* ================                                           TIM2                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief General-purpose-timers (TIM2)
  */

typedef struct {                                /*!< (@ 0x40000000) TIM2 Structure                                             */
  __IOM uint32_t  CR1;                          /*!< (@ 0x00000000) control register 1                                         */
  __IOM uint32_t  CR2;                          /*!< (@ 0x00000004) control register 2                                         */
  __IOM uint32_t  SMCR;                         /*!< (@ 0x00000008) slave mode control register                                */
  __IOM uint32_t  DIER;                         /*!< (@ 0x0000000C) DMA/Interrupt enable register                              */
  __IOM uint32_t  SR;                           /*!< (@ 0x00000010) status register                                            */
  __OM  uint32_t  EGR;                          /*!< (@ 0x00000014) event generation register                                  */
  
  union {
    __IOM uint32_t CCMR1_Output;                /*!< (@ 0x00000018) capture/compare mode register 1 (output mode)              */
    __IOM uint32_t CCMR1_Input;                 /*!< (@ 0x00000018) capture/compare mode register 1 (input mode)               */
  };
  
  union {
    __IOM uint32_t CCMR2_Output;                /*!< (@ 0x0000001C) capture/compare mode register 2 (output mode)              */
    __IOM uint32_t CCMR2_Input;                 /*!< (@ 0x0000001C) capture/compare mode register 2 (input mode)               */
  };
  __IOM uint32_t  CCER;                         /*!< (@ 0x00000020) capture/compare enable register                            */
  __IOM uint32_t  CNT;                          /*!< (@ 0x00000024) counter                                                    */
  __IOM uint32_t  PSC;                          /*!< (@ 0x00000028) prescaler                                                  */
  __IOM uint32_t  ARR;                          /*!< (@ 0x0000002C) auto-reload register                                       */
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  CCR1;                         /*!< (@ 0x00000034) capture/compare register 1                                 */
  __IOM uint32_t  CCR2;                         /*!< (@ 0x00000038) capture/compare register 2                                 */
  __IOM uint32_t  CCR3;                         /*!< (@ 0x0000003C) capture/compare register 3                                 */
  __IOM uint32_t  CCR4;                         /*!< (@ 0x00000040) capture/compare register 4                                 */
  __IM  uint32_t  RESERVED1;
  __IOM uint32_t  DCR;                          /*!< (@ 0x00000048) DMA control register                                       */
  __IOM uint32_t  DMAR;                         /*!< (@ 0x0000004C) DMA address for full transfer                              */
  __IOM uint32_t  OR1;                          /*!< (@ 0x00000050) TIM option register                                        */
  __IM  uint32_t  RESERVED2[3];
  __IOM uint32_t  AF1;                          /*!< (@ 0x00000060) TIM alternate function option register 1                   */
  __IM  uint32_t  RESERVED3;
  __IOM uint32_t  TISEL;                        /*!< (@ 0x00000068) TIM alternate function option register 1                   */
} TIM2_Type;                                    /*!< Size = 108 (0x6c)                                                         */



/* =========================================================================================================================== */
/* ================                                           NVIC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Nested Vectored Interrupt  Controller (NVIC)
  */

typedef struct {                                /*!< (@ 0xE000E100) NVIC Structure                                             */
  __IOM uint32_t  ISER;                         /*!< (@ 0x00000000) Interrupt Set Enable Register                              */
  __IM  uint32_t  RESERVED[31];
  __IOM uint32_t  ICER;                         /*!< (@ 0x00000080) Interrupt Clear Enable Register                            */
  __IM  uint32_t  RESERVED1[31];
  __IOM uint32_t  ISPR;                         /*!< (@ 0x00000100) Interrupt Set-Pending Register                             */
  __IM  uint32_t  RESERVED2[31];
  __IOM uint32_t  ICPR;                         /*!< (@ 0x00000180) Interrupt Clear-Pending Register                           */
  __IM  uint32_t  RESERVED3[95];
  __IOM uint32_t  IPR0;                         /*!< (@ 0x00000300) Interrupt Priority Register 0                              */
  __IOM uint32_t  IPR1;                         /*!< (@ 0x00000304) Interrupt Priority Register 1                              */
  __IOM uint32_t  IPR2;                         /*!< (@ 0x00000308) Interrupt Priority Register 2                              */
  __IOM uint32_t  IPR3;                         /*!< (@ 0x0000030C) Interrupt Priority Register 3                              */
  __IOM uint32_t  IPR4;                         /*!< (@ 0x00000310) Interrupt Priority Register 4                              */
  __IOM uint32_t  IPR5;                         /*!< (@ 0x00000314) Interrupt Priority Register 5                              */
  __IOM uint32_t  IPR6;                         /*!< (@ 0x00000318) Interrupt Priority Register 6                              */
  __IOM uint32_t  IPR7;                         /*!< (@ 0x0000031C) Interrupt Priority Register 7                              */
  __IOM uint32_t  IPR8;                         /*!< (@ 0x00000320) Interrupt Priority Register 8                              */
} NVIC_Type;                                    /*!< Size = 804 (0x324)                                                        */



/* =========================================================================================================================== */
/* ================                                            MPU                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Memory protection unit (MPU)
  */

typedef struct {                                /*!< (@ 0xE000ED90) MPU Structure                                              */
  __IM  uint32_t  MPU_TYPER;                    /*!< (@ 0x00000000) MPU type register                                          */
  __IM  uint32_t  MPU_CTRL;                     /*!< (@ 0x00000004) MPU control register                                       */
  __IOM uint32_t  MPU_RNR;                      /*!< (@ 0x00000008) MPU region number register                                 */
  __IOM uint32_t  MPU_RBAR;                     /*!< (@ 0x0000000C) MPU region base address register                           */
  __IOM uint32_t  MPU_RASR;                     /*!< (@ 0x00000010) MPU region attribute and size register                     */
} MPU_Type;                                     /*!< Size = 20 (0x14)                                                          */



/* =========================================================================================================================== */
/* ================                                            STK                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief SysTick timer (STK)
  */

typedef struct {                                /*!< (@ 0xE000E010) STK Structure                                              */
  __IOM uint32_t  CSR;                          /*!< (@ 0x00000000) SysTick control and status register                        */
  __IOM uint32_t  RVR;                          /*!< (@ 0x00000004) SysTick reload value register                              */
  __IOM uint32_t  CVR;                          /*!< (@ 0x00000008) SysTick current value register                             */
  __IOM uint32_t  CALIB;                        /*!< (@ 0x0000000C) SysTick calibration value register                         */
} STK_Type;                                     /*!< Size = 16 (0x10)                                                          */



/* =========================================================================================================================== */
/* ================                                            SCB                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief System control block (SCB)
  */

typedef struct {                                /*!< (@ 0xE000ED00) SCB Structure                                              */
  __IM  uint32_t  CPUID;                        /*!< (@ 0x00000000) CPUID base register                                        */
  __IOM uint32_t  ICSR;                         /*!< (@ 0x00000004) Interrupt control and state register                       */
  __IOM uint32_t  VTOR;                         /*!< (@ 0x00000008) Vector table offset register                               */
  __IOM uint32_t  AIRCR;                        /*!< (@ 0x0000000C) Application interrupt and reset control register           */
  __IOM uint32_t  SCR;                          /*!< (@ 0x00000010) System control register                                    */
  __IOM uint32_t  CCR;                          /*!< (@ 0x00000014) Configuration and control register                         */
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  SHPR2;                        /*!< (@ 0x0000001C) System handler priority registers                          */
  __IOM uint32_t  SHPR3;                        /*!< (@ 0x00000020) System handler priority registers                          */
} SCB_Type;                                     /*!< Size = 36 (0x24)                                                          */



/* =========================================================================================================================== */
/* ================                                          VREFBUF                                          ================ */
/* =========================================================================================================================== */


/**
  * @brief System configuration controller (VREFBUF)
  */

typedef struct {                                /*!< (@ 0x40010030) VREFBUF Structure                                          */
  __IOM uint32_t  CSR;                          /*!< (@ 0x00000000) VREFBUF control and status register                        */
  __IOM uint32_t  CCR;                          /*!< (@ 0x00000004) VREFBUF calibration control register                       */
} VREFBUF_Type;                                 /*!< Size = 8 (0x8)                                                            */



/* =========================================================================================================================== */
/* ================                                            DBG                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief MCU debug component (DBG)
  */

typedef struct {                                /*!< (@ 0x40015800) DBG Structure                                              */
  __IM  uint32_t  IDCODE;                       /*!< (@ 0x00000000) DBGMCU_IDCODE                                              */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000004) Debug MCU configuration register                           */
  __IOM uint32_t  APB_FZ1;                      /*!< (@ 0x00000008) Debug MCU APB1 freeze register1                            */
  __IOM uint32_t  APB_FZ2;                      /*!< (@ 0x0000000C) Debug MCU APB1 freeze register 2                           */
} DBG_Type;                                     /*!< Size = 16 (0x10)                                                          */



/* =========================================================================================================================== */
/* ================                                         NVIC_STIR                                         ================ */
/* =========================================================================================================================== */


/**
  * @brief Nested vectored interrupt  controller (NVIC_STIR)
  */

typedef struct {                                /*!< (@ 0xE000EF00) NVIC_STIR Structure                                        */
  __IOM uint32_t  STIR;                         /*!< (@ 0x00000000) Software trigger interrupt register                        */
} NVIC_STIR_Type;                               /*!< Size = 4 (0x4)                                                            */



/* =========================================================================================================================== */
/* ================                                         SCB_ACTRL                                         ================ */
/* =========================================================================================================================== */


/**
  * @brief System control block ACTLR (SCB_ACTRL)
  */

typedef struct {                                /*!< (@ 0xE000E008) SCB_ACTRL Structure                                        */
  __IOM uint32_t  ACTRL;                        /*!< (@ 0x00000000) Auxiliary control register                                 */
} SCB_ACTRL_Type;                               /*!< Size = 4 (0x4)                                                            */



/* =========================================================================================================================== */
/* ================                                         FPU_CPACR                                         ================ */
/* =========================================================================================================================== */


/**
  * @brief Floating point unit CPACR (FPU_CPACR)
  */

typedef struct {                                /*!< (@ 0xE000ED88) FPU_CPACR Structure                                        */
  __IOM uint32_t  CPACR;                        /*!< (@ 0x00000000) Coprocessor access control register                        */
} FPU_CPACR_Type;                               /*!< Size = 4 (0x4)                                                            */



/* =========================================================================================================================== */
/* ================                                            FPU                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Floting point unit (FPU)
  */

typedef struct {                                /*!< (@ 0xE000EF34) FPU Structure                                              */
  __IOM uint32_t  FPCCR;                        /*!< (@ 0x00000000) Floating-point context control register                    */
  __IOM uint32_t  FPCAR;                        /*!< (@ 0x00000004) Floating-point context address register                    */
  __IOM uint32_t  FPSCR;                        /*!< (@ 0x00000008) Floating-point status control register                     */
} FPU_Type;                                     /*!< Size = 12 (0xc)                                                           */



/* =========================================================================================================================== */
/* ================                                       SYSCFG_ITLINE                                       ================ */
/* =========================================================================================================================== */


/**
  * @brief System configuration controller (SYSCFG_ITLINE)
  */

typedef struct {                                /*!< (@ 0x40010080) SYSCFG_ITLINE Structure                                    */
  __IM  uint32_t  RESERVED[32];
  __IM  uint32_t  ITLINE0;                      /*!< (@ 0x00000080) interrupt line 0 status register                           */
  __IM  uint32_t  ITLINE1;                      /*!< (@ 0x00000084) interrupt line 1 status register                           */
  __IM  uint32_t  ITLINE2;                      /*!< (@ 0x00000088) interrupt line 2 status register                           */
  __IM  uint32_t  ITLINE3;                      /*!< (@ 0x0000008C) interrupt line 3 status register                           */
  __IM  uint32_t  ITLINE4;                      /*!< (@ 0x00000090) interrupt line 4 status register                           */
  __IM  uint32_t  ITLINE5;                      /*!< (@ 0x00000094) interrupt line 5 status register                           */
  __IM  uint32_t  ITLINE6;                      /*!< (@ 0x00000098) interrupt line 6 status register                           */
  __IM  uint32_t  ITLINE7;                      /*!< (@ 0x0000009C) interrupt line 7 status register                           */
  __IM  uint32_t  RESERVED1;
  __IM  uint32_t  ITLINE9;                      /*!< (@ 0x000000A4) interrupt line 9 status register                           */
  __IM  uint32_t  ITLINE10;                     /*!< (@ 0x000000A8) interrupt line 10 status register                          */
  __IM  uint32_t  ITLINE11;                     /*!< (@ 0x000000AC) interrupt line 11 status register                          */
  __IM  uint32_t  ITLINE12;                     /*!< (@ 0x000000B0) interrupt line 12 status register                          */
  __IM  uint32_t  ITLINE13;                     /*!< (@ 0x000000B4) interrupt line 13 status register                          */
  __IM  uint32_t  ITLINE14;                     /*!< (@ 0x000000B8) interrupt line 14 status register                          */
  __IM  uint32_t  ITLINE15;                     /*!< (@ 0x000000BC) interrupt line 15 status register                          */
  __IM  uint32_t  ITLINE16;                     /*!< (@ 0x000000C0) interrupt line 16 status register                          */
  __IM  uint32_t  ITLINE17;                     /*!< (@ 0x000000C4) interrupt line 17 status register                          */
  __IM  uint32_t  ITLINE18;                     /*!< (@ 0x000000C8) interrupt line 18 status register                          */
  __IM  uint32_t  ITLINE19;                     /*!< (@ 0x000000CC) interrupt line 19 status register                          */
  __IM  uint32_t  RESERVED2;
  __IM  uint32_t  ITLINE21;                     /*!< (@ 0x000000D4) interrupt line 21 status register                          */
  __IM  uint32_t  ITLINE22;                     /*!< (@ 0x000000D8) interrupt line 22 status register                          */
  __IM  uint32_t  ITLINE23;                     /*!< (@ 0x000000DC) interrupt line 23 status register                          */
  __IM  uint32_t  ITLINE24;                     /*!< (@ 0x000000E0) interrupt line 24 status register                          */
  __IM  uint32_t  ITLINE25;                     /*!< (@ 0x000000E4) interrupt line 25 status register                          */
  __IM  uint32_t  ITLINE26;                     /*!< (@ 0x000000E8) interrupt line 26 status register                          */
  __IM  uint32_t  ITLINE27;                     /*!< (@ 0x000000EC) interrupt line 27 status register                          */
  __IM  uint32_t  ITLINE28;                     /*!< (@ 0x000000F0) interrupt line 28 status register                          */
  __IM  uint32_t  ITLINE29;                     /*!< (@ 0x000000F4) interrupt line 29 status register                          */
  __IM  uint32_t  RESERVED3;
  __IM  uint32_t  ITLINE31;                     /*!< (@ 0x000000FC) interrupt line 31 status register                          */
} SYSCFG_ITLINE_Type;                           /*!< Size = 256 (0x100)                                                        */


/** @} */ /* End of group Device_Peripheral_peripherals */


/* =========================================================================================================================== */
/* ================                          Device Specific Peripheral Address Map                           ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripheralAddr
  * @{
  */

#define IWDG_BASE                   0x40003000UL
#define WWDG_BASE                   0x40002C00UL
#define FLASH_BASE                  0x40022000UL
#define RCC_BASE                    0x40021000UL
#define PWR_BASE                    0x40007000UL
#define DMA_BASE                    0x40020000UL
#define DMAMUX_BASE                 0x40020800UL
#define GPIOA_BASE                  0x50000000UL
#define GPIOB_BASE                  0x50000400UL
#define GPIOC_BASE                  0x50000800UL
#define GPIOD_BASE                  0x50000C00UL
#define GPIOF_BASE                  0x50001400UL
#define AES_BASE                    0x40026000UL
#define RNG_BASE                    0x40025000UL
#define CRC_BASE                    0x40023000UL
#define EXTI_BASE                   0x40021800UL
#define TIM16_BASE                  0x40014400UL
#define TIM17_BASE                  0x40014800UL
#define USART1_BASE                 0x40013800UL
#define USART2_BASE                 0x40004400UL
#define SPI1_BASE                   0x40013000UL
#define SPI2_BASE                   0x40003800UL
#define TIM1_BASE                   0x40012C00UL
#define ADC_BASE                    0x40012400UL
#define SYSCFG_BASE                 0x40010000UL
#define TAMP_BASE                   0x4000B000UL
#define LPTIM1_BASE                 0x40007C00UL
#define LPTIM2_BASE                 0x40009400UL
#define LPUART_BASE                 0x40008000UL
#define I2C1_BASE                   0x40005400UL
#define I2C2_BASE                   0x40005800UL
#define RTC_BASE                    0x40002800UL
#define TIM14_BASE                  0x40002000UL
#define TIM2_BASE                   0x40000000UL
#define TIM3_BASE                   0x40000400UL
#define NVIC_BASE                   0xE000E100UL
#define MPU_BASE                    0xE000ED90UL
#define STK_BASE                    0xE000E010UL
#define SCB_BASE                    0xE000ED00UL
#define VREFBUF_BASE                0x40010030UL
#define DBG_BASE                    0x40015800UL
#define NVIC_STIR_BASE              0xE000EF00UL
#define SCB_ACTRL_BASE              0xE000E008UL
#define FPU_CPACR_BASE              0xE000ED88UL
#define FPU_BASE                    0xE000EF34UL
#define SYSCFG_ITLINE_BASE          0x40010080UL

/** @} */ /* End of group Device_Peripheral_peripheralAddr */


/* =========================================================================================================================== */
/* ================                                  Peripheral declaration                                   ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_declaration
  * @{
  */

#define IWDG                        ((IWDG_Type*)              IWDG_BASE)
#define WWDG                        ((WWDG_Type*)              WWDG_BASE)
#define FLASH                       ((FLASH_Type*)             FLASH_BASE)
#define RCC                         ((RCC_Type*)               RCC_BASE)
#define PWR                         ((PWR_Type*)               PWR_BASE)
#define DMA                         ((DMA_Type*)               DMA_BASE)
#define DMAMUX                      ((DMAMUX_Type*)            DMAMUX_BASE)
#define GPIOA                       ((GPIOA_Type*)             GPIOA_BASE)
#define GPIOB                       ((GPIOB_Type*)             GPIOB_BASE)
#define GPIOC                       ((GPIOB_Type*)             GPIOC_BASE)
#define GPIOD                       ((GPIOB_Type*)             GPIOD_BASE)
#define GPIOF                       ((GPIOB_Type*)             GPIOF_BASE)
#define AES                         ((AES_Type*)               AES_BASE)
#define RNG                         ((RNG_Type*)               RNG_BASE)
#define CRC                         ((CRC_Type*)               CRC_BASE)
#define EXTI                        ((EXTI_Type*)              EXTI_BASE)
#define TIM16                       ((TIM16_Type*)             TIM16_BASE)
#define TIM17                       ((TIM16_Type*)             TIM17_BASE)
#define USART1                      ((USART1_Type*)            USART1_BASE)
#define USART2                      ((USART1_Type*)            USART2_BASE)
#define SPI1                        ((SPI1_Type*)              SPI1_BASE)
#define SPI2                        ((SPI1_Type*)              SPI2_BASE)
#define TIM1                        ((TIM1_Type*)              TIM1_BASE)
#define ADC                         ((ADC_Type*)               ADC_BASE)
#define SYSCFG                      ((SYSCFG_Type*)            SYSCFG_BASE)
#define TAMP                        ((TAMP_Type*)              TAMP_BASE)
#define LPTIM1                      ((LPTIM1_Type*)            LPTIM1_BASE)
#define LPTIM2                      ((LPTIM1_Type*)            LPTIM2_BASE)
#define LPUART                      ((LPUART_Type*)            LPUART_BASE)
#define I2C1                        ((I2C1_Type*)              I2C1_BASE)
#define I2C2                        ((I2C1_Type*)              I2C2_BASE)
#define RTC                         ((RTC_Type*)               RTC_BASE)
#define TIM14                       ((TIM14_Type*)             TIM14_BASE)
#define TIM2                        ((TIM2_Type*)              TIM2_BASE)
#define TIM3                        ((TIM2_Type*)              TIM3_BASE)
#define NVIC                        ((NVIC_Type*)              NVIC_BASE)
#define MPU                         ((MPU_Type*)               MPU_BASE)
#define STK                         ((STK_Type*)               STK_BASE)
#define SCB                         ((SCB_Type*)               SCB_BASE)
#define VREFBUF                     ((VREFBUF_Type*)           VREFBUF_BASE)
#define DBG                         ((DBG_Type*)               DBG_BASE)
#define NVIC_STIR                   ((NVIC_STIR_Type*)         NVIC_STIR_BASE)
#define SCB_ACTRL                   ((SCB_ACTRL_Type*)         SCB_ACTRL_BASE)
#define FPU_CPACR                   ((FPU_CPACR_Type*)         FPU_CPACR_BASE)
#define FPU                         ((FPU_Type*)               FPU_BASE)
#define SYSCFG_ITLINE               ((SYSCFG_ITLINE_Type*)     SYSCFG_ITLINE_BASE)

/** @} */ /* End of group Device_Peripheral_declaration */


/* =========================================  End of section using anonymous unions  ========================================= */
#if defined (__CC_ARM)
  #pragma pop
#elif defined (__ICCARM__)
  /* leave anonymous unions enabled */
#elif (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic pop
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning restore
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#endif


#ifdef __cplusplus
}
#endif

#endif /* STM32G030_H */


/** @} */ /* End of group STM32G030 */

/** @} */ /* End of group  */
